Google is a leading technology company focused on shaping the future of AI and Infrastructure. They are seeking an ASIC Design Verification Engineer to drive the development of custom silicon solutions that power Google's AI/ML applications, specifically focusing on TPU architecture and its integration within AI/ML-driven systems.
Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios
Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
Identify and write all types of coverage measures for stimulus and corner-cases
Debug tests with design engineers to deliver correct design blocks
Close coverage measures to identify verification holes and to show progress towards tape-out
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
1 year of experience in design verification
Experience with SystemVerilog/Verilog
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
Experience with Universal Verification Methodology (UVM) testbenches and methodologies
Experience developing and executing test plans
Familiarity with coverage analysis tools (e.g., Verdi, Questa)
Proficiency in SystemVerilog, including object-oriented programming, SystemVerilog Assertions (SVAs) and functional coverage
Excellent problem-solving and debugging skills
Benefits
Bonus
Equity
Benefits
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
