ASIC RTL Design Engineer, ML Accelerators

Sunnyvale, CA

Full-time

Onsite

$132K/yr - $189K/yr

Entry, Mid Level

Google is a leading technology company that is shaping the future of AI/ML hardware acceleration. In this role, you will develop custom silicon solutions for TPU technology, contributing to the design and verification of complex digital designs within AI/ML-driven systems.

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Responsibilities

Develop SystemVerilog RTL to implement logic for ASIC products
Create and review design microarchitecture specifications
Work with design validation (DV) teams to create testplans to verify, and debug design RTL
Work with physical design teams to ensure design meets physical requirements and timing closure

Qualification

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
2 years of experience with RTL design
Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols
Experience in Verilog or SystemVerilog

Preferred

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
5 years of experience in silicon engineering
Experience designing high speed digital designs
Experience optimizing designs for Performance, Power or Area (PPA)
Proficiency in scripting languages such as Python or Perl

Benefits

Bonus
Equity
Benefits

Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.

Glassdoor

4.4

Founded in 1998

Mountain View, California, USA

10001+ employees

https://www.google.com

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