Google is a leading technology company that is shaping the future of AI/ML hardware acceleration. In this role, you will work as an IP DFT Engineer, focusing on defining and implementing design-for-test methodologies for digital or mixed-signal chips, contributing to the innovation behind Google's TPU technology and its integration within AI/ML-driven systems.
Complete Test Design Rule Checks (TDRC) and design changes to fix violations to achieve test quality
Drive design and integration of DFT logic in Test Chips including IEEE1149.1 TAP controller, Boundary Scan, scan chains, MBIST, Clock Control block, and other DFT IP blocks
Insert and connect MBIST logic, including test collars around memories, MBIST controllers, and electronic fuse (eFuse) logic, to core and Test Access Port (TAP) interfaces
Design Verification of DFT logic and test pattern generation
Develop DFT timing constraints in Synopsys Design Constraints (SDC) for DFT logic
Qualification
Required
Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience
1 year of experience in DFT architecture, implementation, Automatic Test Pattern Generation (ATPG), and verification for SoCs
Preferred
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT)
Benefits
15% bonus target
Equity
Benefits
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
