Google is a leading technology company that is shaping the future of AI/ML hardware acceleration. In this role, you will contribute to the development of custom silicon solutions for TPU technology, collaborating with various teams to optimize performance, power, and area for complex digital designs.
Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS
Collaborate with internal logic and internal and external teams to achieve the best power/performance analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
2 years of experience with physical design (e.g., from RTL to GDSII, including key stages like floor planning, place and route, and timing closure)
Experience in Python, Tcl, or Perl scripting
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
Experience with Synopsys/Cadence PnR tools and backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.)
Experience working with external partners on physical design (PD) closure
Experience in static timing analysis (STA), with an understanding of how to define timing corners, margins and derates
Understanding of DFT including Scan, MBIST and LBIST
Understanding of performance, power and area (PPA) trade-offs
Benefits
Bonus
Equity
Benefits
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
