Google specializes in internet-related services and products, including search, advertising, and software. In this role, you’ll work on shaping the future of AI/ML hardware acceleration, focusing on the physical implementation of ASICs and static timing methodologies.
Debug and resolve common STA or design rule issues like unconstrained endpoints, maximum transition, minimum period, or minimum pulse width violations.
Perform sub chip static timing analysis, timing ECO creation for timing convergence, and final timing sign-off for ASIC tape outs.
Utilize Perl, Python, Tcl, or Bash to create static timing flow automation scripts.
Own and maintain Primetime STA flows.
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in static timing analysis.
Experience in Primetime or Tempus Tcl scripting and static timing analysis debug and problem solving.
Experience in sub chip timing sign-off checklist criteria and overseeing final timing sign-off for ASICs.
Preferred
Experience writing, reviewing and verifying complex Tcl constraints for static timing analysis.
Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
Experience working with multiple foundries.
Knowledge of semiconductor device physics and transistor characteristics.
Benefits
Bonus
Equity
Benefits
Google specializes in internet-related services and products, including search, advertising, and software. It is a sub-organization of Alphabet.
