Google is a leading technology company that is shaping the future of AI/ML hardware acceleration. In this role, you will work on developing custom silicon solutions for Google's Tensor Processing Units (TPUs), focusing on microarchitecture, design, implementation, and integration of digital logic blocks.
Define and document the microarchitecture for digital designs within the TPU
Write high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog
Collaborate with partner teams to support integration efforts and Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness. Support post-silicon validation and debug efforts
Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements
Contribute to the development and enhancement of design tools, flows, and methodologies
Qualification
Required
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
1 year of experience in RTL design
Experience with digital design and microarchitecture design
Cross-functional experience with DV and PD teams
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
4 years of RTL design experience
4 years of RTL design experience and architecting RTL solutions
Experience with Linting, CDC, RDC, LEC
Experience with Scripting languages (i.e. Python or Perl)
