RTL Design Engineer, Google

Sunnyvale, CA

Full-time

Onsite

$116K/yr - $165K/yr

Entry Level

Google is hiring an RTL Design Engineer to design SoC-level RTL for data center accelerators, including infrastructure IP such as fabric bridges and sensor telemetry networks. The role also contributes to SoC infrastructure and methodology and works cross-functionally with software, system hardware, architecture, power, validation, and physical design teams.

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Responsibilities

Create and review clock control subsystem's design micro-architecture specifications
Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines
Work with architecture and power teams to evaluate features and their impact
Work with Design Validation (DV) teams to create test plans to verify and debug design RTL
Work with physical design teams to ensure design meets physical requirements and timing closure

Qualification

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
Experience in SystemVerilog for creating microarchitecture specifications and synthesizable RTL
Experience using Python, Tcl, or Perl for automating design tasks and data analysis
Experience with industry-standard EDA tools for simulation, synthesis, and power analysis
Experience in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development

Preferred

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
2 years of experience with high-performance ASIC design in Phase-Locked Loop, Frequency-Locked Loop, and Delay-Locked Loop integration
Experience implementing clock skipping, dynamic voltage and frequency scaling (DVFS), and fine-grained clock gating for low-power SoC optimization
Experience utilizing AI productivity tools to streamline individual, business or development workflows
Proficiency in Python or Perl for automating design scripts and analyzing clock-tree data
Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion