Silicon Engineer, PhD, University Graduate, 2027 Start

Sunnyvale, CA

Full-time

Onsite

$138K/yr - $197K/yr

New Grad, Mid Level

Google is seeking a Silicon Engineer to help shape AI and machine learning hardware acceleration through custom silicon and TPU technology. The role involves collaborating across hardware and software teams to research, design, model, simulate, and verify AI accelerators and related systems, with projects tailored to the candidate’s expertise.

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Responsibilities

Responsibilities and projects will be determined based on your background, interest, and skills
Collaborate cross-functionally across hardware and software teams to research, design, and model custom silicon solutions and AI accelerators
Develop, simulate, and verify architectural features, digital blocks, or subsystem interfaces targeting performance, power, and area optimizations
Contribute to EDA design automation flows, tooling infrastructure, or post-silicon bring-up and characterization

Qualification

Required

PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
Experience in any one domain of silicon engineering through internships, academic research, or publications: architecture and RTL, verification and validation, physical design and circuits, systems, test or CAD
Experience with one of the hardware description languages (e.g., Verilog, SystemVerilog) or programming (e.g., Python, Tcl, Perl, or C++)

Preferred

Research experience in specialized areas such as high-performance/low-power architectures, domain-specific accelerators (DSAs/TPUs), memory hierarchies, coherent interconnects (e.g., CXL, PCIe, UCIe, NoC), or advanced packaging/chiplets
Experience developing and maintaining CAD/EDA design flows, methodology infrastructure, or applying ML for chip design automation
Understanding of advanced ML/DL model architectures (e.g., Transformers, LLMs) with experience in performance modeling, cycle-accurate simulation, or custom AI accelerator evaluation
Familiarity with industry-standard EDA tools (e.g., from Synopsys, Cadence, Siemens EDA, or emulation/formal platforms)
Demonstrated research track record and ability to work on complex, open-ended problems, with publications in conferences (e.g., ISCA, MICRO, HPCA, ASPLOS, DAC, ICCAD, ISSCC, NeurIPS, MLSys)