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Silicon Physical Design Engineer

Sunnyvale, CA
Full-time
Onsite
$116K/yr - $166K/yr
Entry Level
Google is seeking a Silicon Physical Design Engineer to shape the future of AI/ML hardware acceleration. In this role, you will drive cutting-edge TPU technology and collaborate with various teams to develop custom silicon solutions that enhance Google's AI/ML applications.
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Responsibilities

  • Participate in the Physical Design (PD) of blocks for complex TPU chips
  • Contribute to the design and closure of the subchip and individual blocks from RTL-to-GDS
  • Collaborate with RTL/Design and PD teams to achieve the best PPA possible, including conducting feasibility studies for new microarchitectures as well as optimizing runs for best Quality of Results (QoR)
  • Create and maintain policies, processes, procedures, methods, tests, and documentation of silicon deliverables for the purpose of enhancing and promoting high efficiency, productivity, and sustainability
  • Identify test requirements, select appropriate tools, methods, and approach, and carry out testing of Silicon systems, influence designs to enable and enhance testing, validation, and debugging

Qualification

Required

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 1 year of experience with physical design
  • Experience with scripting languages such as Perl, Python, or Tcl
  • Experience with Synopsys/Cadence PnR tools and backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.)
  • Experience in static timing analysis (STA), including experience defining timing corners, margins, and derates

Preferred

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
  • Experience with constraints, synthesis or clock tree synthesis (CTS)
  • Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC design
  • Experience working with external partners on physical design (PD) closure
  • Understanding of DFT including Scan, MBIST and LBIST
  • Understanding of performance, power and area (PPA) trade-offs

Benefits

  • 15% bonus target
  • Equity
  • Benefits
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