TPU SoC Design Engineer, Google Cloud

Sunnyvale, CA

Full-time

Onsite

$116K/yr - $166K/yr

Entry Level

Google is a leading technology company, and they are seeking a TPU SoC Design Engineer to shape the future of AI/ML hardware acceleration. The role involves driving cutting-edge TPU technology, developing custom silicon solutions, and collaborating with various ASIC development teams to ensure efficient design and implementation.

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Responsibilities

Define and document the microarchitecture for digital designs within the TPU
Write performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog
Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness
Work with the Physical Design team to meet timing, area, power, and manufacturability requirements
Contribute to the development and enhancement of design tools, flows, and methodologies

Qualification

Required

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience
2 years of experience in ASIC RTL design using systemverilog or verilog
Experience with industry-standard EDA tools for simulation, synthesis, and power analysis
Experiecnce with digital design, including synchronous and asynchronous logic, state machines, and bus protocols

Preferred

Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture
5 years of experience with RTL coding using Verilog/SystemVerilog
Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS
Experience with SOC implementation standards and interfaces (e.g., AXI)
Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL
Experience with CDC, UPF, RDC, RTL Linting, and LEC